| Analysis and Design of a Passive Switched-Capacitor Matrix Multiplier for Approximate Computing. | 3 | 0.41 | 2017 |
| Fault-Tolerant FPGA with Column-Based Redundancy and Power Gating Using RRAM. | 0 | 0.34 | 2017 |
| 24.2 A 2.5GHz 7.7TOPS/W switched-capacitor matrix multiplier with co-designed local memory in 40nm. | 3 | 0.43 | 2016 |
| TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits. | 14 | 0.60 | 2016 |
| Compact One-Transistor-N-RRAM Array Architecture for Advanced CMOS Technology | 6 | 0.99 | 2015 |
| Factorization For Analog-To-Digital Matrix Multiplication | 3 | 0.78 | 2015 |
| Monolithic 3-D FPGAs | 1 | 0.35 | 2015 |
| Effect of Wordline/Bitline Scaling on the Performance, Energy Consumption, and Reliability of Cross-Point Memory Array | 3 | 0.40 | 2013 |
| Impact of III–V and Ge Devices on Circuit Performance | 0 | 0.34 | 2013 |
| Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory. | 55 | 5.15 | 2012 |
| A 65 nm CMOS fully-integrated dynamic reconfigurable differential power amplifier with high gain in both bands | 0 | 0.34 | 2011 |
| Array Architecture for a Nonvolatile 3-Dimensional Cross-Point Resistance-Change Memory. | 4 | 0.74 | 2011 |
| Modeling and analysis of III–V logic FETs for devices and circuits: Sub-22nm technology III–V SRAM cell design | 0 | 0.34 | 2010 |
| Pi Coil: A New Element for Bandwidth Extension | 0 | 0.34 | 2009 |
| The Prospect Of 3d-Ic | 1 | 0.50 | 2009 |
| Reduction of Inductive Crosstalk Using Quadrupole Inductors | 4 | 0.63 | 2009 |
| Pi coil: a new element for bandwidth extension | 1 | 0.48 | 2009 |
| Optimization of Driver Preemphasis for On-Chip Interconnects | 4 | 0.60 | 2009 |
| Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation | 25 | 1.73 | 2008 |
| Closed-Form RC and RLC Delay Models Considering Input Rise Time. | 9 | 0.90 | 2007 |
| Performance Benefits of Monolithically Stacked 3-D FPGA | 29 | 1.48 | 2007 |
| A Fully Integrated RF Front-End with Independent RX/TX Matching and +20dBm Output Power for WLAN Applications. | 5 | 1.32 | 2007 |
| Near speed-of-light signaling over on-chip electrical interconnects | 49 | 6.22 | 2003 |
| On the Accuracy of Return Path Assumption for Loop Inductance Extraction for 0.1µm Technology and Beyond | 5 | 0.64 | 2003 |
| Design of a 10GHz clock distribution network using coupled standing-wave oscillators | 16 | 1.81 | 2003 |
| On-Chip Interconnect Inductance - Friend or Foe (Invited) | 3 | 0.51 | 2003 |
| A 10-GHz global clock distribution using coupled standing-wave oscillators | 55 | 6.35 | 2003 |
| High-Frequency Characterization Of On-Chip Digital Interconnects | 18 | 1.74 | 2002 |
| CMOS RF integrated circuits at 5 GHz and beyond | 9 | 2.85 | 2000 |
| Design strategy of on-chip inductors for highly integrated RF systems | 7 | 1.50 | 1999 |
