Paper Info
Title
Panel session what is the electronics industry doing to win the battle against the expected scary failure rates in future technology nodes?
Abstract
The major bottleneck for technology scaling is the growing rate of hardware failures. Process variations are becoming extreme and sensitivity to radiation is becoming severe. In addition, intrinsic failures such as device parameter degradation are accelerating the wear-out. All of these are leading to higher random in-filed failures and shorter device lifetime. The 2011 ITRS (International Technology Roadmap for Semiconductors) projects very high bit failure rates of the order of 10−2 for SRAM and of 10−3 for latches for 16nm high performance technology. Hence, solving reliability challenges for future technologies requires new efficient and cost effective approaches not only to detect and recover from in-filed failures, but also to extend the device lifetime for targeted applications. The panel session aims at gathering opinions from electronics industry on the above challenges and discuss some strategic approaches to provide resilience against intrinsic, random and extrinsic failures. Some questions we hope to be answered are: • Is the electronics industry already facing any reliability issues? How big is the problem? • What is the industry using today to realize reliable and robust systems? Is this going to changes soon? • Can reliability problems prevent using smaller technology nodes in run-time and safety critical applications? • How is reliability evaluation done today? Are there any tools? • Are reliability problems going to become server with technology scaling? Can we quantify? • What is industry doing to prepare themselves and prevent the scary expected failure rates? • Do they need a deep understanding of the technology in order to provide efficient solutions? • What is the best approach to use (bottom-up or top-down)? • Etc.
Year
DOI
Venue
2013
10.1109/ETS.2013.6569360
ETS
Keywords
Field
DocType
hardware,electronics industry,reliability,sensitivity
Psychological resilience,Bottleneck,Technology scaling,Telecommunications,Computer science,Knowledge management,Risk analysis (engineering),International Technology Roadmap for Semiconductors,Electronics,Battle
Conference
ISBN
Citations 
PageRank 
978-1-4673-6376-1
0
0.34
References 
Authors
0
8
Name
Order
Citations
PageRank
Said Hamdioui1887118.69
Davide Appello2378.48
Arnaud Grasset311710.09
Xinli Gu Huawei400.34
Bram Kruseman522317.48
Riccardo Mariani65210.08
Hermann Obermeir7151.24
Srikanth Venkataraman857248.05