| A Survey on Memory-centric Computer Architectures | 0 | 0.34 | 2022 |
| CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out | 1 | 0.35 | 2022 |
| Reliability Analysis of FinFET-Based SRAM PUFs for 16nm, 14nm, and 7nm Technology Nodes | 0 | 0.34 | 2022 |
| Energy-Efficient SNN Implementation Using RRAM-Based Computation In-Memory (CIM) | 0 | 0.34 | 2022 |
| Smart Redundancy Schemes for ANNs Against Fault Attacks | 0 | 0.34 | 2022 |
| A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs | 0 | 0.34 | 2022 |
| MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design. | 0 | 0.34 | 2022 |
| Exploiting PUF Variation to Detect Fault Injection Attacks | 0 | 0.34 | 2022 |
| Would Magnonic Circuits Outperform CMOS Counterparts? | 0 | 0.34 | 2022 |
| Rapid Design-Space Exploration for Low-Power Manycores Under Process Variation Utilizing Machine Learning | 0 | 0.34 | 2022 |
| Improving the Detection of Undefined State Faults in FinFET SRAMs | 0 | 0.34 | 2021 |
| Intermittent Undefined State Fault in RRAMs | 2 | 0.45 | 2021 |
| Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM | 0 | 0.34 | 2021 |
| Low-Power Memristor-Based Computing For Edge-Ai Applications | 0 | 0.34 | 2021 |
| Emerging Computing Devices: Challenges and Opportunities for Test and Reliability * | 1 | 0.36 | 2021 |
| LightRoAD: Lightweight Rowhammer Attack Detector | 0 | 0.34 | 2021 |
| Revealing the Secrets of Spiking Neural Networks: The Case of Izhikevich Neuron | 0 | 0.34 | 2021 |
| Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions | 1 | 0.35 | 2021 |
| Impact of Data Pre-Processing Techniques on Deep Learning Based Power Attacks | 0 | 0.34 | 2021 |
| Evaluation Of Single Event Upset Susceptibility Of Finfet-Based Srams With Weak Resistive Defects | 0 | 0.34 | 2021 |
| GRINCH - A Cache Attack against GIFT Lightweight Cipher. | 0 | 0.34 | 2021 |
| Defect and Fault Modeling Framework for STT-MRAM Testing | 1 | 0.36 | 2021 |
| Review of Manufacturing Process Defects and Their Effects on Memristive Devices | 1 | 0.37 | 2021 |
| Review of Manufacturing Process Defects and Their Effects on Memristive Devices | 1 | 0.37 | 2021 |
| Multi-Bit Blinding: A Countermeasure for RSA Against Side Channel Attacks | 0 | 0.34 | 2021 |
| Deterministic and Statistical Strategies to Protect ANNs against Fault Injection Attacks | 0 | 0.34 | 2021 |
| Skeleton-based Synthesis Flow for Computation-In-Memory Architectures | 0 | 0.34 | 2020 |
| On the Analysis of Real-time Operating System Reliability in Embedded Systems | 0 | 0.34 | 2020 |
| A Security Verification Template to Assess Cache Architecture Vulnerabilities | 0 | 0.34 | 2020 |
| 4-output Programmable Spin Wave Logic Gate | 0 | 0.34 | 2020 |
| RNN-Based Detection of Fault Attacks on RSA | 0 | 0.34 | 2020 |
| Efficient Organization of Digital Periphery to Support Integer Datatype for Memristor-Based CIM | 1 | 0.35 | 2020 |
| LiD-CAT: A Lightweight Detector for Cache ATtacks | 0 | 0.34 | 2020 |
| eSRAM Reliability: Why is it still not optimally solved? | 0 | 0.34 | 2020 |
| Testing Computation-in-Memory Architectures Based on Emerging Memories | 1 | 0.36 | 2019 |
| Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM | 1 | 0.37 | 2019 |
| A computation-in-memory accelerator based on resistive devices | 2 | 0.36 | 2019 |
| System-Level Sub-20 Nm Planar And Finfet Cmos Delay Modelling For Supply And Threshold Voltage Scaling Under Process Variation | 0 | 0.34 | 2019 |
| Rebooting Computing: The Challenges for Test and Reliability | 0 | 0.34 | 2019 |
| Hardware-Based Aging Mitigation Scheme for Memory Address Decoder | 0 | 0.34 | 2019 |
| Efficient Methodology for ISO26262 Functional Safety Verification | 0 | 0.34 | 2019 |
| CIM-SIM: Computation In Memory SIMuIator | 0 | 0.34 | 2019 |
| Impact and mitigation of SRAM read path aging. | 0 | 0.34 | 2018 |
| Ionizing radiation modeling in DRAM transistors | 0 | 0.34 | 2018 |
| State Of The Art And Challenges For Test And Reliability Of Emerging Nonvolatile Resistive Memories | 1 | 0.36 | 2018 |
| A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs. | 1 | 0.38 | 2018 |
| Region based containers — A new paradigm for the analysis of fault tolerant networks | 0 | 0.34 | 2017 |
| Standards-based tools and services for building lifelong learning pathways. | 0 | 0.34 | 2017 |
| Interconnect networks for resistive computing architectures | 0 | 0.34 | 2017 |
| Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier. | 7 | 0.62 | 2017 |
