Name
Abstract | ||
|---|---|---|
This paper introduces a novel half-select resilient dual write wordline 8T (DW8T) SRAM with a sequential writing technique. The dual write wordlines are sequentially activated in a write cycle, and its combination with the half-VDD precharge suppresses the half-select problem. We implemented a 256-Kb DW8T SRAM and a half-VDD generator with a 40-nm CMOS process. The measurement results of the seven samples show that the proposed DW8T SRAM achieves a VDDmin of 600mV and improves the average VDDmin by 367mV compared to the conventional 8T SRAM. The measured leakage power can be reduced by 25%. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1587/elex.9.1023 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
SRAM, 8T, disturb, half-select | Computer science,Leakage power,Static random-access memory,Cmos process,Computer hardware | Journal |
Volume | Issue | ISSN |
9 | 12 | 1349-2543 |
Citations | PageRank | References |
1 | 0.37 | 3 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shusuke Yoshimoto | 1 | 30 | 12.56 |
| Masaharu Terada | 2 | 8 | 2.25 |
| Shunsuke Okumura | 3 | 63 | 12.54 |
| Toshi-kazu Suzuki | 4 | 73 | 11.00 |
| Shinji Miyano | 5 | 85 | 12.63 |
| Hiroshi Kawaguchi | 6 | 37 | 21.08 |
| Masahiko Yoshimoto | 7 | 1 | 0.37 |