Abstract | ||
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An enhanced CPA (correlation power analysis) attack which screens key candidates using correlation levels and ranking is proposed in this paper. An AES circuis is implemented on a Xilinxreg FPGA on SASEBO (side-channel attack standard evaluation board) specifically designed for side-channel attack experiments, and the proposed attack is performed and compared to the standard CPA. As a result, the key screening technique successfully reduces the calculation time for handing 5,000 power traces by 26%. In addition to the accelerated computation, the accuracy of the key estimation is also improved. |
Year | DOI | Venue |
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2008 | 10.1109/ReConFig.2008.16 | ReConFig |
Keywords | Field | DocType |
accelerated computation,aes circuis,key screening technique,side-channel attack standard evaluation,enhanced correlation power analysis,proposed attack,calculation time,key candidate,side-channel attack experiment,correlation level,key estimation,fpga,side channel attacks,side channel attack,field programmable gate arrays,electronics packaging,cryptography,argon,power analysis,correlation | Power analysis,Correlation power analysis,Ranking,Computer science,Cryptography,Field-programmable gate array,Real-time computing,Side channel attack,Computer engineering,Embedded system,Computation | Conference |
ISBN | Citations | PageRank |
978-0-7695-3474-9 | 5 | 0.44 |
References | Authors | |
2 | 5 |
Name | Order | Citations | PageRank |
---|---|---|---|
Toshihiro Katashita | 1 | 128 | 12.53 |
Akashi Satoh | 2 | 866 | 69.99 |
Takeshi Sugawara | 3 | 126 | 12.25 |
Naofumi Homma | 4 | 377 | 53.81 |
Takafumi Aoki | 5 | 915 | 125.99 |