Name
Affiliation
Papers
TAKESHI SUGAWARA
Tohoku Univ, Grad Sch Informat Sci, Sendai, Miyagi, Japan
20
Collaborators
Citations 
PageRank 
32
126
12.25
Referers 
Referees 
References 
294
281
151
Search Limit
100294
Title
Citations
PageRank
Year
Mixture-Based 5-Round Physical Attack against AES: Attack Proposal and Noise Evaluation00.342022
An Abstraction Model For 1-Bit Probing Attack On Block Ciphers00.342019
Side-channel leakage from sensor-based countermeasures against fault injection attack00.342019
Q-Class Authentication System For Double Arbiter Puf00.342018
A Secure LiDAR with AES-Based Side-Channel Fingerprinting00.342018
Exploiting Bitflip Detector for Non-invasive Probing and its Application to Ineffective Fault Analysis00.342017
Evaluation Of Information Leakage From Cryptographic Hardware Via Common-Mode Current10.362012
Fair and consistent hardware evaluation of fourteen round two SHA-3 candidates211.632012
Circuit Simulation for Fault Sensitivity Analysis and Its Application to Cryptographic LSI40.452012
A Configurable On-Chip Glitchy-Clock Generator For Fault Injection Experiments40.432012
High-Performance Architecture For Concurrent Error Detection For Aes Processors00.342011
An on-chip glitchy-clock generator for testing fault injection attacks.90.532011
Profiling Attack Using Multivariate Regression Analysis100.612010
Mechanism behind Information Leakage in Electromagnetic Analysis of Cryptographic Modules50.562009
A High-Resolution Phase-Based Waveform Matching and Its Application to Side-Channel Attacks70.722008
High-Performance Concurrent Error Detection Scheme for AES Hardware391.372008
Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool10.352008
Enhanced Correlation Power Analysis Using Key Screening Technique50.442008
High-performance ASIC implementations of the 128-bit block cipher CLEFIA70.772008
High-Speed Parallel Hardware Architecture for Galois Counter Mode131.652007