Name
Abstract | ||
|---|---|---|
In this paper we describe a parameterizable FPGA-based implementation of a sigma-delta converter used in a 96kHz audio DAC. From specifications of the converter's input bitwidth and data sampling frequency, VHDL generic parameters are used to automatically generate the required design. The resulting implementation is optimized to use the minimum internal wordlength and number of stages. We prototyped the converter on an FPGA board for verification purposes and the results are presented. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1007/978-3-540-30117-2_54 | Lecture Notes in Computer Science |
Keywords | Field | DocType |
sampling frequency | System-level simulation,Computer science,Sampling (signal processing),Field-programmable gate array,Circuit design,Delta-sigma modulation,Noise shaping,VHDL,Hardware description language,Embedded system | Conference |
Volume | ISSN | Citations |
3203 | 0302-9743 | 0 |
PageRank | References | Authors |
0.34 | 1 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ralf Ludewig | 1 | 12 | 3.56 |
| Oliver Soffke | 2 | 6 | 3.63 |
| Peter Zipf | 3 | 186 | 45.00 |
| Manfred Glesner | 4 | 1121 | 255.04 |
| Kong Pang Pun | 5 | 0 | 1.01 |
| K. H. Tsoi | 6 | 399 | 38.79 |
| Kin-Hong Lee | 7 | 257 | 26.27 |
| Philip H.W. Leong | 8 | 849 | 101.45 |