Name
Title | ||
|---|---|---|
Circuit Simulation for Fault Sensitivity Analysis and Its Application to Cryptographic LSI |
Abstract | ||
|---|---|---|
Circuit simulation method for Fault Sensitivity Analysis (FSA) is proposed. The simulation can be used both for (i) security evaluation before fabrication and (ii) investigation of leak mechanism. The proposed method extracts fault sensitivity data from post place-and-route logic simulation results, thus it can easily be integrated with conventional LSI design flow. As a proof of concept, the proposed method is applied to netlist of an AES implementation on 130-nm SASEBO LSI. In the experiment, key recovery attack is successfully recreated using simulated data of a standard implementation (AES_Comp). In addition, to bridge a gap between the simulation and real measurement, we model the effect of induced timing jitter (measurement noise) on the resulting correlation. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/FDTC.2012.17 | FDTC |
Keywords | Field | DocType |
post place-and-route logic simulation,aes implementation,sensitivity data,measurement noise,conventional lsi design flow,proposed method extracts fault,circuit simulation method,130-nm sasebo lsi,real measurement,circuit simulation,cryptographic lsi,fault sensitivity analysis,data models,logic circuits,side channel attacks,indexes,logic simulation,integrated circuit design,histograms,cryptography,network routing | Netlist,Logic gate,Computer science,Design flow,Real-time computing,Integrated circuit design,Logic simulation,Side channel attack,Jitter,AES implementations | Conference |
Citations | PageRank | References |
4 | 0.45 | 9 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Takeshi Sugawara | 1 | 126 | 12.25 |
| Daisuke Suzuki | 2 | 306 | 21.80 |
| Toshihiro Katashita | 3 | 128 | 12.53 |