Name
Abstract | ||
|---|---|---|
This paper justifies the use of estimation and prediction of carries to increase the performance of functional units built with the replication of full adders while keeping a low area penalization. Adders and multipliers are the most representative modules in this group of functional units. The use of these design techniques allows the implementation of modules with performance improvements ranging from 20% to 50% with only an area overheads around 5%. These functional units are suitable for asynchronous circuits but they could also be introduced in synchronous circuits with speculative techniques. The basic idea consists in estimating the carry out from some parts of the functional units, allowing every part to operate independently and in parallel. These modules are connected to build bigger ones. Results from simulations show that for some applications it is possible to make predictions even more accurate that the bit-based estimation. Predictions have also the advantage they can be introduced in the multipliers design, whether estimators cannot. These predictions are similar to the ones used in the branch prediction in a processor. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ICCD.2008.4751843 | ICCD |
Keywords | Field | DocType |
logic design,asynchronous circuit,adders,estimation,branch prediction,functional unit,history,current transformers | Logic synthesis,Asynchronous communication,Current transformer,Adder,Computer science,Parallel computing,Real-time computing,Ranging,Electronic circuit,Branch predictor,Estimator | Conference |
ISSN | ISBN | Citations |
1063-6404 E-ISBN : 978-1-4244-2658-4 | 978-1-4244-2658-4 | 7 |
PageRank | References | Authors |
0.67 | 7 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alberto A. Del Barrio | 1 | 78 | 14.49 |
| María C. Molina | 2 | 77 | 6.97 |
| Jose Manuel Mendias | 3 | 17 | 2.77 |
| Esther Andres Perez | 4 | 7 | 0.67 |
| Román Hermida | 5 | 89 | 15.34 |
| Francisco Tirado | 6 | 36 | 3.36 |