Name
Abstract | ||
|---|---|---|
Nowadays, design issues related to physical design and scalability are becoming the main bottlenecks of modern tools for technology mapping, limiting the usage of large cells. On the other hand, the generation of regular macro cells, such as compound gates, are becoming interesting from the manufacturing point of view, but they need to be properly integrated into the existing industrial design flows. In this paper, we present an efficient methodology for identifying the cells that can extend an existing standard-cell library. We validated our approach on different benchmarks targeting area minimization and we also analyzed timing, power consumption and routing effects for the final circuit implementation. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/ISVLSI.2010.69 | ISVLSI |
Keywords | Field | DocType |
efficient methodology,existing industrial design flow,fast heuristic,large cell,different benchmarks,regular macro cells,area minimization,compound gate,physical design,existing standard-cell library,final circuit implementation,extending standard cell libraries,design issue,minimisation,data structures,logic gates,transistors,industrial design,logic synthesis,boolean functions,network routing,integrated circuit design | Logic synthesis,Industrial design,Heuristic,Computer science,Integrated circuit design,Standard cell,Physical design,Macro,Distributed computing,Embedded system,Scalability | Conference |
ISSN | ISBN | Citations |
2159-3469 | 978-1-4244-7321-2 | 1 |
PageRank | References | Authors |
0.39 | 12 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Christian Pilato | 1 | 329 | 32.19 |
| Fabrizio Ferrandi | 2 | 548 | 56.95 |
| Davide Pandini | 3 | 94 | 15.76 |