Name
Title | ||
|---|---|---|
Trapped charge and stress induced leakage current (SILC) in tunnel SiO2 layers of de-processed MOS non-volatile memory devices observed at the nanoscale |
Abstract | ||
|---|---|---|
In this work, Conductive Atomic Force Microscope (CAFM) experiments have been combined with device level measurements to evaluate the impact of an electrical stress applied on MOS structures with a 9.8nm thick SiO2 layer for memory devices. Charge trapping in the generated defects and leakage current measured at the nanoscale have been correlated to the measurements obtained on fully processed MOS structures. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1016/j.microrel.2009.06.016 | Microelectronics Reliability |
Keywords | Field | DocType |
non volatile memory,leakage current,atomic force microscope,stress induced leakage current | Nanoscopic scale,Atomic force microscopy,Leakage (electronics),Electrical conductor,Electronic engineering,Trapping,Non-volatile memory,Engineering,Integrated circuit,SILC | Journal |
Volume | Issue | ISSN |
49 | 9 | 0026-2714 |
Citations | PageRank | References |
0 | 0.34 | 1 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| M. Lanza | 1 | 1 | 1.30 |
| M. Porti | 2 | 5 | 3.78 |
| M. Nafría | 3 | 60 | 7.58 |
| X. Aymerich | 4 | 21 | 12.21 |
| G. Ghidini | 5 | 7 | 6.21 |
| A. Sebastiani | 6 | 0 | 1.35 |