Paper Info
Title
Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection
Abstract
System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and high-performance integration of heterogeneous chip technologies and to support robust chip manufacturing with high-yield/low-cost chips for a wide range of two- and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. High-density wiring and high-density chip I/O interconnection can enable tight integration of heterogeneous chip technologies which approximate the performance of an integrated system-on-chip with a "virtual chip" using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density chip microbump interconnections scale to smaller size. In addition to heterogeneous chip integration, SOP products may leverage the integration of passive components, active devices, and electro-optic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications.
Year
DOI
Venue
2005
10.1147/rd.494.0725
IBM Journal of Research and Development
Keywords
Field
DocType
high-density chip,silicon through-vias,next-generation system-on-package,high-density chip microbump interconnection,heterogeneous chip integration,low-cost chip,heterogeneous chip technology,robust chip manufacturing,good chip,silicon carrier,silicon package,fine-pitch chip interconnection,o chip interconnection,chip
System on a chip,Computer science,Chip,Electronic engineering,CMOS,Modular design,Interconnection,Electronic component,Chip-scale package,Silicon
Journal
Volume
Issue
ISSN
49
4/5
0018-8646
Citations 
PageRank 
References 
28
9.29
7
Authors
20
Name
Order
Citations
PageRank
J. U. Knickerbocker112431.11
P. S. Andry210622.38
L. P. Buchwalter3289.29
A. Deutsch412893.73
R. R. Horton59918.83
K. A. Jenkins6289.29
Y. H. Kwark73111.14
McVicker, G.83610.35
C. S. Patel918822.62
R. J. Polastre109718.50
C. Schuster11289.29
A. Sharma12289.29
S. M. Sri-Jayantha137414.07
C. W. Surovic148445.71
C. K. Tsang1510622.38
B. C. Webb1610622.38
S. L. Wright17289.29
S. R. McKnight18289.29
E. J. Sprogis1912824.81
Dang, B.2011022.83