Paper Info
Title
A Test Integration Methodology for 3D Integrated Circuits
Abstract
The three-dimensional (3D) integration technology using through silicon via (TSV) provides many benefits over the 2D integration technology. Although many different manufacturing technologies for 3D integrated circuits (ICs) have been presented, some challenges should be overcome before the volume production of 3D ICs. One of the challenges is the testing of 3D ICs. This paper proposes test integration interfaces for controlling the design-for-test circuits in the dies of a 3D IC. The test integration interfaces can support the pre-bond, known-good stack, and post-bond tests. The minimum number of required test pads of the proposed test interface for pre-bond test using is only four. Furthermore, the test interface is compatible with the IEEE 1149.1 standard for the board-level testing. Simulation results show that the area overhead of the proposed test interfaces for a 3D IC with two dies in which each die implements the function of ITC’99 b19 benchmark is only about 0.15%.
Year
DOI
Venue
2010
10.1109/ATS.2010.71
Asian Test Symposium
Keywords
Field
DocType
test integration methodology,test integration interface,post-bond test,integrated circuits,test interface,pre-bond test,required test pad,board-level testing,proposed test interface,integration technology,different manufacturing technology,area overhead,strontium,design for test,test,integration testing,three dimensional,registers,switches,through silicon via,testing,3d,circuits,3d ic
Computer science,Automatic test equipment,Electronic engineering,Through-silicon via,Die (manufacturing),Three-dimensional integrated circuit,Electronic circuit,Integrated circuit
Conference
ISSN
Citations 
PageRank 
1081-7735
9
0.66
References 
Authors
21
6
Name
Order
Citations
PageRank
Che-Wei Chou1323.59
Jin-Fu Li266259.17
Ji-Jan Chen31169.34
Ding-Ming Kwai452146.85
Yung-Fa Chou524423.76
Wu, Cheng-Wen61843170.44