Name
Abstract | ||
|---|---|---|
A partitioning methodology between the reconfigurable hardware blocks of different granularity, which are embedded in a generic heterogeneous architecture, is presented. The fine-grain reconfigurable logic is realized by an FPGA unit, while the coarse-grain reconfigurable hardware by a 2-Dimensional Array of Processing Elements. Critical parts, called kernels, are mapped on the coarse-grain reconfigurable logic for improving performance. The partitioning method is mainly composed by three steps: the analysis of the input code, the mapping onto the Coarse-Grain Reconfigurable Array and the mapping onto the FPGA. The partitioning flow is implemented by a prototype software framework. Analytical partitioning experiments, using five real-world applications, show that the execution time speedup relative to an all-FPGA solution ranges from 1.4 to 5.0. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1007/s11227-006-6743-5 | The Journal of Supercomputing |
Keywords | Field | DocType |
heterogeneous reconfigurable architectures,performance improvements,partitioning,coarse-grain reconfigurable hardware,FPGA,scheduling | Supercomputer,Computer science,Scheduling (computing),Parallel computing,Field-programmable gate array,Granularity,Vector processor,Software framework,Reconfigurable computing,Speedup | Journal |
Volume | Issue | ISSN |
38 | 1 | 0920-8542 |
Citations | PageRank | References |
6 | 0.47 | 19 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michalis D. Galanis | 1 | 94 | 15.60 |
| Gregory Dimitroulakos | 2 | 47 | 7.14 |
| Costas E Goutis | 3 | 186 | 25.76 |