Paper Info
Title
One-Shot Reed-Solomon Decoding for High-Performance Dependable Systems
Abstract
This paper presents a scheme of ultra-fast one-shot Reed-Solomon decoding (prototyped (40-34,32,8) soft-IP demonstrating over 7 Gb/s using 0.35 μm ASIC technology) and discusses its application to future dependable computer systems, taking a redundant array memory system as an example. We compare different memory configurations and identify improved fault-tolerance to single-bit failures as well as chip and card failures for smaller system overheads when random quad-byte one-shot Reed-Solomon decoding is used. We also discuss an alternative use of the powerful coding gain, i.e., an application to the dynamic refresh interval control of DRAMs, in order to optimize the refresh overheads in performance and power consumption. We believe that the one-shot Reed-Solomon decoding offers an advanced error correction capability for various parts of future high-performance computer systems, where system-level reliability can suffer because of rapidly increasing data size and speed
Year
DOI
Venue
2000
10.1109/ICDSN.2000.857567
New York, NY
Keywords
Field
DocType
different memory configuration,dynamic refresh interval control,ultra-fast one-shot reed-solomon decoding,smaller system overhead,future high-performance computer system,high-performance dependable systems,random quad-byte one-shot reed-solomon,one-shot reed-solomon decoding,future dependable computer system,refresh overhead,redundant array memory system,chip,fault tolerant,application specific integrated circuits,prototypes,decoding,coding gain,error correction,reed solomon,application software,fault tolerance,performance
Dram,Coding gain,Computer science,Reed–Solomon error correction,Real-time computing,Error detection and correction,Chip,Decoding methods,Overhead (business),Embedded system,Power consumption
Conference
ISBN
Citations 
PageRank 
0-7695-0707-7
4
0.68
References 
Authors
9
2
Name
Order
Citations
PageRank
Yasunao Katayama18517.18
Sumio Morioka249345.23