Name
Abstract | ||
|---|---|---|
This article proposes a new methodology for enhancing SoC signal integrity without degrading performance in the presence of power-ground voltage transients. The underlying principle is the dynamic adaptation of the clock duty cycle to propagation delay variation along disturbed logic paths. This methodology makes digital circuits more robust to power line fluctuations while maintaining the at-speed clock rate. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/MDT.2008.146 | IEEE Design & Test of Computers |
Keywords | Field | DocType |
signal integrity enhancement,new methodology,digital circuit,at-speed clock rate,disturbed logic path,digital circuits,soc signal integrity,dynamic adaptation,degrading performance,delay variation,clock duty cycle,power line fluctuation,duty cycle,signal generators,signal integrity,frequency,rlc circuits,system on a chip,voltage,propagation delay,system on chip | Clock signal,Propagation delay,Digital signal,Computer science,Signal integrity,Clock domain crossing,Electronic engineering,Digital clock manager,Asynchronous circuit,Clock rate | Journal |
Volume | Issue | ISSN |
25 | 5 | 0740-7475 |
Citations | PageRank | References |
1 | 0.35 | 0 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jorge Filipe L. C. Semião | 1 | 1 | 0.35 |
| Marcial Jesús Rodríguez Irago | 2 | 1 | 0.35 |
| J. Rodriguez-Andina | 3 | 237 | 30.29 |
| Leonardo Bisch Piccoli | 4 | 1 | 0.35 |
| Fabian Luis Vargas | 5 | 1 | 0.69 |
| Marcelino B. Santos | 6 | 129 | 20.76 |
| I. C. Teixeira | 7 | 163 | 20.29 |
| João Paulo Teixeira | 8 | 140 | 22.06 |