Name
Abstract | ||
|---|---|---|
A low power monolithic Clock and Data Recovery IC for 2.5 Gb/s SDH STM-16 systems has been designed and fabricated using Maxim GST-2 27 GHz-fT Silicon bipolar technology. The circuit performs the following functions: signal amplification and limitation, clock recovery and decision; a single 3.3 V supply voltage is required, and power consumption results below 350 mW. This IC and a previously presented transimpedance amplifier so allows composing a chip set for the receiver with a total power dissipation below 0.5 W. Preliminary measurements under a 223-1 PRBS data stream have shown an input sensitivity below 20 mVpp and a rms jitter of 10 ps. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1145/344166.344202 | ISLPED |
Keywords | Field | DocType |
low power,ghz-ft silicon bipolar technology,v supply voltage,maxim gst-2,prbs data stream,data recovery ic,sdh receiver,low-power clock,total power dissipation,w. preliminary measurement,data recovery circuit,power consumption result,sdh stm-16 system,transimpedance amplifier,chip,voltage,synchronisation,silicon,optical communications,power dissipation,optical communication,pll | Synchronization,Clock recovery,Data stream,Computer science,Voltage,Electronic engineering,Transimpedance amplifier,Jitter,Data recovery,Chipset,Electrical engineering | Conference |
ISBN | Citations | PageRank |
1-58113-190-9 | 0 | 0.34 |
References | Authors | |
5 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Andrea Pallotta | 1 | 1 | 0.77 |
| Francesco Centurelli | 2 | 56 | 15.93 |
| A. Trifiletti | 3 | 433 | 63.29 |