Paper Info
Title
Accurate Area, Time and Power Models for FPGA-Based Implementations
Abstract
This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family (Deng et al. 2008). These models are designed to facilitate efficient design space exploration in an automated algorithm-architecture codesign framework. Detailed models for estimating the number of slices, block RAMs and 18脳18-bit multipliers for fixed point and floating point IP cores have been developed. These models are also utilized to develop power models that consider the effect of logic power, signal power, clock power and I/O power. Timing models have been developed to predict the latency of the fixed point and floating point IP cores. In all cases, the model coefficients have been derived by using curve fitting or regression analysis. The modeling error is quite small for single IP cores; the error for the area estimate, for instance, is on the average 0.95%. The error for fairly large examples such as floating point implementation of 8-point FFTs is also quite small; it is 1.87% for estimation of number of slices and 3.48% for estimation of power consumption. The proposed models have also been integrated into a hardware-software partitioning tool to facilitate design space exploration under area and time constraints.
Year
DOI
Venue
2011
10.1007/s11265-009-0387-7
Signal Processing Systems
Keywords
Field
DocType
FPGA,Estimators for area,Time,Power,IP core,Regression analysis,Design space exploration
Curve fitting,Computer science,Floating point,Latency (engineering),Regression analysis,Parallel computing,Field-programmable gate array,Implementation,Real-time computing,Fixed point,Design space exploration
Journal
Volume
Issue
ISSN
63
1
1939-8018
Citations 
PageRank 
References 
14
0.89
19
Authors
4
Name
Order
Citations
PageRank
Lanping Deng1685.91
Kanwaldeep Sobti2514.23
Yuanrui Zhang318015.48
Chaitali Chakrabarti41978184.17