Abstract | ||
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Recently there are various requirements for LSI testing, such as test compaction, test compression, low power dissipation or increase of defect coverage. If test sequences contain lots of don't cares (Xs), then their flexibility can be used to meet the above requirements. In this paper, we propose methods for finding as many Xs as possible in test sequences for sequential circuits. Given a fully specified test sequence generated by a sequential ATPG, the proposed methods produce a test sequence containing Xs without losing stuck-at fault coverage of the original test sequence. The methods apply an approach based on fault simulation, and they introduce some heuristics for reducing the simulation effort. Experimental results for ISCAS'89 benchmark circuits show the effectiveness of the proposed methods. |
Year | DOI | Venue |
---|---|---|
2006 | 10.1093/ietisy/e89-d.11.2748 | IEICE Transactions |
Keywords | Field | DocType |
sequential circuits,sequential circuit,sequential atpg,test compaction,test sequences,defect coverage,simulation effort,fault simulation,test compression,original test sequence,test sequence | Stuck-at fault,Automatic test pattern generation,Test method,Sequential logic,Fault coverage,Computer science,Algorithm,Heuristics,Test compression,Integrated circuit | Journal |
Volume | Issue | ISSN |
E89-D | 11 | 1745-1361 |
Citations | PageRank | References |
4 | 0.47 | 0 |
Authors | ||
5 |
Name | Order | Citations | PageRank |
---|---|---|---|
Yoshinobu Higami | 1 | 140 | 27.24 |
Seiji Kajihara | 2 | 989 | 73.60 |
Irith Pomeranz | 3 | 3829 | 336.84 |
Shin-ya Kobayashi | 4 | 38 | 8.60 |
Yuzo Takamatsu | 5 | 150 | 27.40 |