Paper Info
Title
Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism
Abstract
In this paper a systematic mapping method for a specific algorithm class is given which exploits all levels of parallelism of the target architecture. This target architecture is a processor array where each processing element can have several functional units. This functional units allow subword parallelism, that means multiple equal operations with low data word width can be executed in parallel in the data path of the functional units. The mapping method is illustrated on the edge detection algorithm, and achieves up to 99 % of the theoretical speed-up.
Year
DOI
Venue
2008
10.1109/DSD.2008.24
DSD
Keywords
Field
DocType
subword parallelism,systematic mapping method,mapping method,functional unit,data path,edge detection algorithm,specific algorithm class,target architecture,low data word width,processor array,multiple equal operation,computer architecture,design methods,edge detection,parallel processing,parallel algorithms,design method,algorithm design and analysis
Instruction-level parallelism,Algorithm design,Implicit parallelism,Computer science,Parallel algorithm,Processor array,Task parallelism,Parallel computing,Data parallelism,Word (computer architecture)
Conference
Citations 
PageRank 
References 
0
0.34
14
Authors
4
Name
Order
Citations
PageRank
Rainer Schaffer1295.30
Renate Merker215920.59
Frank Hannig359575.66
Jürgen Teich42886273.54