Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism | 0 | 0.34 | 2008 |
Massively Parallel Processor Architectures: A Co-design Approach | 1 | 0.36 | 2007 |
Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels | 0 | 0.34 | 2006 |
Derivation of Packing Instructions for Exploiting Sub-Word Parallelism | 2 | 0.38 | 2006 |
An Architecture Description Language for Massively Parallel Processor Architectures. | 5 | 0.53 | 2006 |
Co-Design of Massively Parallel Embedded Processor Architectures | 9 | 0.67 | 2005 |
A Parallel Hardware-Software System for Signal Processing Algorithms | 0 | 0.34 | 2004 |
A Hardware-Software System for Tomographic Reconstruction | 2 | 0.67 | 2003 |
Causality Constraints for Processor Architectures with Sub-Word Parallelism | 2 | 0.39 | 2003 |
Systematic Design of Programs with Sub-Word Parallelism | 5 | 0.50 | 2002 |
Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel | 1 | 0.38 | 2000 |
COMBINING BACKGROUND MEMORY MANAGEMENT AND REGULAR ARRAY CO-PARTITIONING, ILLUSTRATED ON A FULL MOTION ESTIMATION KERNEL | 2 | 0.41 | 2000 |