Name
Abstract | ||
|---|---|---|
In recent VLSIs, small-delay defects, which are hard to detect by traditional delay fault testing, can bring about serious issues such as short lifetime. To detect small-delay defects, on-chip delay measurement which measures the delay time of paths in the circuit under test (CUT) was proposed. However, this approach incurs high test cost because it uses scan design, which brings about long test application time due to scan shift operation. Our solution is a test application time reduction method for testing using the on-chip path delay measurement. The testing with on-chip path delay measurement does not require capture operations, unlike the conventional delay testing. Specifically, FFs keep the transition pattern of the test pattern pair sensitizing a path under measurement (PUM) (denoted as p) even after the measurement of p. The proposed method uses this characteristic. The proposed method reduces scan shift time and test data volume using test pattern merging. Evaluation results on ISCAS89 benchmark circuits indicate that the proposed method reduces the test application time by 6.89 similar to 62.67% and test data volume by 46.39 similar to 74.86%. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1587/transinf.E97.D.533 | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS |
Keywords | Field | DocType |
small-delay defects, test compaction, test application time, test data volume, on-chip delay measurement | Computer science,Test compaction,Computer hardware,Shift time | Journal |
Volume | Issue | ISSN |
E97D | 3 | 1745-1361 |
Citations | PageRank | References |
1 | 0.46 | 17 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wenpo Zhang | 1 | 1 | 1.14 |
| Kazuteru Namba | 2 | 114 | 27.93 |
| Hideo Ito | 3 | 100 | 17.45 |