Name
Title | ||
|---|---|---|
Acceleration of Transition Test Generation for Acyclic Sequential Circuits Utilizing Constrained Combinational Stuck-At Test Generation |
Abstract | ||
|---|---|---|
An unified gate-level fault model for interconnect opens and bridges is proposed. Defects are modeled as constrained multiple line stuck-at faults. A novel feature of the proposed fault model is its flexibility to accommodate increasing levels of accuracy. ... |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ETS.2005.4 | European Test Symposium |
Keywords | Field | DocType |
unified gate-level fault model,novel feature,proposed fault model,acyclic sequential circuits utilizing,constrained combinational stuck-at test,transition test generation,multiple line stuck-at fault,equivalent circuits,doubling time,sequential circuits,combinational circuits,sequential analysis,automatic test pattern generation | Automatic test pattern generation,Generation time,Sequential logic,Logic testing,Computer science,Algorithm,Electronic engineering,Combinational logic,Acceleration,Equivalent circuit | Conference |
ISBN | Citations | PageRank |
0-7695-2341-2 | 3 | 0.41 |
References | Authors | |
16 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tsuyoshi Iwagaki | 1 | 29 | 8.42 |
| Satoshi Ohtake | 2 | 135 | 21.62 |
| Hideo Fujiwara | 3 | 264 | 28.05 |