Name
Abstract | ||
|---|---|---|
Controlling the chip temperature is becoming one of the important design considerations, since temperature adversely and seriously affects many of design qualities, such as reliability, performance and power of chip, and increases the packaging cost. In this work, we address a new problem of thermal-aware functional module binding in high-level synthesis, in which the objective is to minimize the peak temperature of the chip. Two key contributions are (1) to solve the binding problem with the primary objective of minimizing the "peak" switched capacitance of modules and the secondary objective of minimizing the "total" switched capacitance of modules and (2) to control the switched capacitances with respect to the floorplan of modules in a way to minimize the "peak" heat diffusion between modules. For (1), our proposed thermal- aware binding algorithm, called TA-b, formulates the thermal-aware binding problem into a problem of repeated utilization of network flow method, and solve it effectively. For (2), TA-b is extended, called TA-bf, to take into account a given floorplan information of functional modules, if exists, of modules to be practically effective. Through experiments using a set of benchmarks, it is shown that TA-bf is able to use 10.1 degrees C and 11.8 degrees C lower peak temperature on the average, compared to that of the conventional low-power and thermal- aware methods, which target to minimizing total switched capacitance only in Ref. 20 and to minimizing peak switched capacitance only in Ref. 16, respectively. Additionally, we confirm, from the experiments, that the reduced peak temperature saves leakage power significantly, implying that controlling chip temperature is critically important for reducing leakage current as well. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1142/S0218126609005472 | JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS |
Keywords | Field | DocType |
Embedded system design,switching capacitance,temperature,leakage power | Flow network,Thermal,Leakage (electronics),Computer science,High-level synthesis,Electronic engineering,Chip,Heat equation,Binding problem,Floorplan | Journal |
Volume | Issue | ISSN |
18 | 5 | 0218-1266 |
Citations | PageRank | References |
8 | 0.52 | 12 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pilok Lim | 1 | 18 | 1.12 |
| Ki-seok Chung | 2 | 189 | 18.76 |
| Taewhan Kim | 3 | 1087 | 113.31 |