Name
Abstract | ||
|---|---|---|
The emerging SOI technologies provide an increased body bias range compared to traditional bulk technologies, opening new opportunities. From the power management perspective, a new degree of freedom is added to the supply voltage and clock frequency variation, increasing the complexity of the power optimization problem. In this paper, a method is proposed to manage the power consumed in an FD-SOI circuit through supply and body bias voltages, and clock frequency variation. Results for a Digital Signal Processor in STMicroelectronics 28nm FD-SOI technology show that the power reduction ratio can reach 17%. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1145/2593069.2593185 | Design Automation Conference |
Keywords | Field | DocType |
energy efficiency,resource pooling | Silicon on insulator,Power management,Power optimization,Digital signal processor,Computer science,Voltage,Real-time computing,Electronic engineering,Electronic circuit,Electrical engineering,Clock rate,Biasing | Conference |
ISSN | Citations | PageRank |
0738-100X | 5 | 0.58 |
References | Authors | |
12 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yeter Akgul | 1 | 5 | 0.92 |
| Diego Puschini | 2 | 71 | 10.76 |
| Suzanne Lesecq | 3 | 111 | 20.60 |
| Edith Beigne | 4 | 536 | 52.54 |
| Ivan Miro-Panades | 5 | 86 | 6.16 |
| P. Benoit | 6 | 74 | 12.39 |
| Lionel Torres | 7 | 346 | 53.92 |