Name
Title | ||
|---|---|---|
A self-testing and calibration method for embedded successive approximation register ADC |
Abstract | ||
|---|---|---|
This paper presents a self-testing and calibration method for the embedded successive approximation register (SAR) analog-to-digital converter (ADC). We first propose a low cost design-for-test (DfT) technique which tests a SAR ADC by characterizing its digital-to-analog converter (DAC) capacitor array. Utilizing DAC major carrier transition testing, the required analog measurement range is just 4 LSBs; this significantly lowers the test circuitry complexity. Then, we develop a fully-digital missing code calibration technique that utilizes the proposed testing scheme to collect the required calibration information. Simulation results are presented to validate the proposed technique.
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Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ASPDAC.2011.5722279 | ASP-DAC |
Keywords | Field | DocType |
sar adc,calibration method,proposed testing scheme,fully-digital missing code calibration,embedded successive approximation register,digital-to-analog converter,proposed technique,utilizing dac major carrier,required analog measurement range,required calibration information,analog-to-digital converter,calibration,switches,design for testability,design for test,capacitors,system on a chip,linearity,testing | Design for testing,Capacitor,System on a chip,Computer science,Linearity,Automatic testing,Shaping,Real-time computing,Electronic engineering,Successive approximation ADC,Calibration | Conference |
ISSN | ISBN | Citations |
2153-6961 | 978-1-4244-7516-2 | 5 |
PageRank | References | Authors |
0.56 | 4 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xuan-Lun Huang | 1 | 23 | 5.33 |
| Ping-Ying Kang | 2 | 10 | 1.56 |
| Hsiu-Ming (Sherman) Chang | 3 | 31 | 3.78 |
| Jiun-Lang Huang | 4 | 263 | 35.90 |
| Yung-Fa Chou | 5 | 244 | 23.76 |
| Yung-Pin Lee | 6 | 100 | 17.18 |
| Ding-Ming Kwai | 7 | 521 | 46.85 |
| Wu, Cheng-Wen | 8 | 1843 | 170.44 |