Name
Abstract | ||
|---|---|---|
With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. A possible solution to alleviate this problem in the future could consist in using fault tolerant architectures to tolerate manufacturing defects. In this paper, we analyze the conditions that make the use of a classical Triple Modular Redundancy (TMR) architecture interesting for a yield improvement purpose. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/IOLTS.2008.10 | IOLTS |
Keywords | Field | DocType |
possible solution,nano dimension,yield improvement,classical triple modular redundancy,fault tolerant architecture,yield improvement purpose,very large scale integration,logic gates,fault tolerant,fault tolerance,robots,testing,transistors,design for testability,hardware,silicon,computer architecture,redundancy,artificial neural networks,error probability,manufacturing | Design for testing,Logic gate,Computer science,Triple modular redundancy,Real-time computing,Fault tolerance,Redundancy (engineering),Transient analysis,Probability of error,Reliability engineering | Conference |
ISSN | Citations | PageRank |
1942-9398 | 4 | 0.90 |
References | Authors | |
3 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| J. Vial | 1 | 26 | 3.06 |
| A. Bosio | 2 | 113 | 15.51 |
| P. Girard | 3 | 478 | 41.91 |
| C. Landrault | 4 | 178 | 13.49 |
| S. Pravossoudovitch | 5 | 689 | 54.12 |
| A. Virazel | 6 | 169 | 23.25 |