Name
Title | ||
|---|---|---|
Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults |
Abstract | ||
|---|---|---|
3-D integration has been touted as an approach to reducing the lengths of critical paths in field-programmable gate arrays (FPGAs). A 3-D chip stacks a number of 2-D FPGA bare dies, interconnected by through-silicon vias (TSVs) and micro bumps, to attain a high packing density. However, the technology also introduces new types of defects, such as TSV void and microbump misalignment. Testing the interconnection faults becomes inevitable. In this paper, we present an automatic test pattern generator for open, short, and delay faults on 3-D FPGA interconnects by exploiting the regularity of switch matrix topology and forming repetitive paths with finite steps and with loop-back. The experimental results show that 12 test patterns (TPs) suffice to achieve 100% open fault coverage (FC). To detect all possible neighboring short faults, we need more than 40 TPs, whose number increases only slightly with the height of the 3-D FPGA. The TPs have high delay FC (96%) for 3-D FPGAs with the number of configurable logic blocks ranging from 50$\,\times\,$ 50$\,\times\,$2 to 50 $\,\times\,$50$\,\times\,$6, demonstrating the scalability of our method. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TVLSI.2013.2242100 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
switch matrix topology,microbump misalignment,integrated circuit testing,field-programmable gate arrays,integrated circuit interconnections,short fault (sf),open fault (of),automatic test pattern generator,application-independent testing,three-dimensional integrated circuits,test patterns,automatic test pattern generation,tsv void,3d integration,fault diagnosis,3-d fpga,interconnect test,3d fpga interconnects,universal test,interconnection faults,field-programmable gate array (fpga) testing,field programmable gate arrays,open fault coverage,configurable logic blocks,through-silicon vias,delay fault | Automatic test pattern generation,Fault coverage,Computer science,Programmable logic array,Field-programmable gate array,Chip,Real-time computing,Electronic engineering,Ranging,Interconnection,Scalability | Journal |
Volume | Issue | ISSN |
22 | 2 | 1063-8210 |
Citations | PageRank | References |
3 | 0.44 | 18 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yen-Lin Peng | 1 | 15 | 1.86 |
| Ding-Ming Kwai | 2 | 521 | 46.85 |
| Yung-Fa Chou | 3 | 244 | 23.76 |
| Wu, Cheng-Wen | 4 | 1843 | 170.44 |