Name
Abstract | ||
|---|---|---|
Compact and high-speed hardware architectures and logic optimization methods for the AES algorithm Rijndael are described. Encryption and decryption data paths are combined and all arithmetic components are reused. By introducing a new composite field, the S-Box structure is also optimized. An extremely small size of 5.4 Kgates is obtained for a 128-bit key Rijndael circuit using a 0.11-µm CMOS standard cell library. It requires only 0.052 mm2 of area to support both encryption and decryption with 311 Mbps throughput. By making effective use of the SPN parallel feature, the throughput can be boosted up to 2.6 Gbps for a high-speed implementation whose size is 21.3 Kgates. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1007/3-540-45682-1_15 | ASIACRYPT |
Keywords | Field | DocType |
128-bit key rijndael circuit,s-box optimization,compact rijndael hardware architecture,arithmetic component,small size,high-speed implementation,mbps throughput,aes algorithm rijndael,spn parallel feature,s-box structure,decryption data path,high-speed hardware architecture,hardware architecture | S-box,Block cipher,Computer science,Advanced Encryption Standard,Encryption,Composite field,Standard cell,AES implementations,Hardware architecture,Embedded system | Conference |
ISBN | Citations | PageRank |
3-540-42987-5 | 268 | 24.82 |
References | Authors | |
12 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Akashi Satoh | 1 | 866 | 69.99 |
| Sumio Morioka | 2 | 493 | 45.23 |
| Kohji Takano | 3 | 425 | 36.67 |
| Seiji Munetoh | 4 | 327 | 33.14 |