Paper Info
Title
Using TMR Architectures for Yield Improvement
Abstract
With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. A possible solution to alleviate this problem in the future could consist in using fault tolerant architectures to tolerate manufacturing defects. In this paper, we use the classical Triple Modular Redundancy (TMR) fault tolerant architecture as a case study. Firstly we analyze the conditions that make the use of TMR architectures interesting for yield improvement purpose. In the second part of the paper, we investigate the test requirements for the TMR architecture and we propose a solution for generating test patterns for this type of architecture. Finally, we propose a new manner to implement the TMR architecture that makes it very effective for yield improvement purpose. Experimental results are provided on ISCAS and ITC benchmark circuits to prove the efficiency of the proposed approach in terms of yield improvement with a low area overhead.
Year
DOI
Venue
2008
10.1109/DFT.2008.23
DFT
Keywords
Field
DocType
test requirement,possible solution,tmr architectures,tmr architecture,yield improvement,classical triple modular redundancy,itc benchmark circuit,fault tolerant architecture,case study,yield improvement purpose,test pattern,manufacturing,fault tolerant,automatic test pattern generation,benchmark testing,triple modular redundancy,fault tolerance,vlsi,computer architecture
Automatic test pattern generation,Architecture,Computer science,Triple modular redundancy,Real-time computing,Fault tolerance,Test requirements,Electronic circuit,Very-large-scale integration,Computer engineering,Benchmark (computing)
Conference
ISSN
Citations 
PageRank 
1550-5774
20
1.65
References 
Authors
9
6
Name
Order
Citations
PageRank
J. Vial1263.06
A. Bosio211315.51
P. Girard347841.91
C. Landrault417813.49
S. Pravossoudovitch568954.12
A. Virazel616923.25