Paper Info
Title
Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs
Abstract
The regularity of resources found in FPGAs is a unique feature, which can be utilized in a number of applications, e.g., in timing critical applications or applications with a demand for homogeneous routing. Current synthesis tools do not support an automatic generation of homogeneous FPGA designs, such that a time-consuming hand-crafted design is required. We present a tool flow, which automatically generates homogeneous hard macros for Xilinx FPGAs starting from a high-level description, such as VHDL. Key functionalities of the tool flow are a homogeneous placer and a suitable routing algorithm, which aim at maintaining the homogeneity of the resulting hard macro. The place and route tools use a resource library that is automatically generated for the target FPGA family by extracting relevant information from the vendor tools. The tool chain is demonstrated for the design of hard macros for a time-to-digital converter and a tiled partially reconfigurable region. The resulting designs are evaluated with respect to resource requirements and timing constraints.
Year
DOI
Venue
2011
10.1109/FCCM.2011.36
Field-Programmable Custom Computing Machines
Keywords
DocType
ISBN
hard macro,tool chain,automatic hdl-based generation,route tool,homogeneous hard macro,tool flow,homogeneous placer,homogeneous fpga design,current synthesis tool,vendor tool,homogeneous routing,homogeneous hard macros,design automation,field programmable gate array,network routing,time to digital converter,vhdl,field programmable gate arrays,reconfigurable computing,routing,registers,place and route,logic design,databases
Conference
978-0-7695-4301-7
Citations 
PageRank 
References 
11
0.95
6
Authors
7
Name
Order
Citations
PageRank
Sebastian Korf1151.77
Dario Cozzi2232.34
Markus Koester3667.39
Jens Hagemeyer4749.47
Mario Porrmann542050.91
U. Rückert6755103.61
Marco D. Santambrogio777191.15