Paper Info
Title
Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays
Abstract
This paper describes a method for algorithm partitioning through which affine indexed algorithms are transformed to Processor Arrays. Former design flows start with a spacetime transformation which we omit completely. Therefore, we are able to consider the constraints of a target architecture at the beginning of our design flow. We show our method for three different partitioning schemes and emphasize on the derivation of a schedule. The principle of an optimized data-reuse is introduced for our partitioning methodology. Under this aspect, we give a parameterized Processor Array for the 2D FIR filter algorithm.
Year
DOI
Venue
2004
10.1109/PCEE.2004.10
PARELEC
Keywords
Field
DocType
different partitioning scheme,design flow,former design flow,parameterized processor array,fir filter algorithm,processor arrays,algorithm partitioning,partitioning methodology,spacetime transformation,optimized data-reuse,information technology,hardware,parallel processing,computer architecture,indexation,finite impulse response filter,algorithm design and analysis,fir filter,fir filters
Affine transformation,Parameterized complexity,Algorithm design,Processor array,Computer science,Spacetime,Parallel computing,Algorithm,Design flow,Finite impulse response,Data reuse
Conference
ISBN
Citations 
PageRank 
0-7695-2080-4
6
0.55
References 
Authors
3
2
Name
Order
Citations
PageRank
Sebastian Siegel1294.16
Renate Merker215920.59