Title
Automatic test program generation for pipelined processors
Abstract
The continuous advances in microelectronics design are creating a significant challenge to design validation in general, but tackling piplined microprocessors is remarkably more demanding. This paper presents a methodology to automatically induce a test program for a microprocessor maximizing a given verification metric. The approach exploits a new evolutionary algorithm, close to Genetic Programming, able to cultivate effective assembly-language programs. The proposed methodology was used to verify the DLX/pII, an open-source processor with a 5-stage pipeline. Code-coverage was adopted in the paper, since it can be considered the required starting point for any simulation-based functional verification processes. Experimental results clearly show the effectiveness of the approach.
Year
DOI
Venue
2003
10.1145/952532.952676
SAC
Keywords
Field
DocType
genetic programming,new evolutionary algorithm,simulation-based functional verification process,proposed methodology,verification metric,automatic test program generation,effective assembly-language program,pipelined processor,continuous advance,5-stage pipeline,microelectronics design,functional verification,genetic algorithms,evolutionary algorithm,code coverage,spanning trees
Functional verification,Evolutionary algorithm,Computer science,Microelectronics,Microprocessor,Parallel computing,Exploit,Genetic programming,Spanning tree,Computer engineering,Genetic algorithm
Conference
ISBN
Citations 
PageRank 
1-58113-624-2
9
1.03
References 
Authors
8
4
Name
Order
Citations
PageRank
F. Corno160255.65
G. Cumani21048.78
M. Sonza Reorda31099114.76
G. Squillero433030.36