Paper Info
Title
Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines
Abstract
The switching behaviour and the operating region of a complementary metal-oxide-semiconductor (CMOS) gate driving a resistance-inductance-capacitance (RLC) transmission line is investigated in this paper. Closed form expressions for the time the transistors operate in the saturation and triode region respectively are proposed. Closed form expressions show predictions within 10% of HSPICE results for a wide range of line and buffer parameters, making them suitable to be applied to the problem of buffer sizing, repeater insertion, short circuit power estimation and generally whenever the accurate knowledge of the operation of CMOS buffers driving a transmission line is required. In the paper useful hints for choosing the most appropriate model for the triode region of the transistors of the inductive-line driver are also given.
Year
DOI
Venue
2002
10.1007/3-540-45716-X_44
PATMOS
Keywords
Field
DocType
accurate knowledge,operating region,cmos gates driving transmission,buffer sizing,transmission line,operating region modelling,appropriate model,paper useful hint,hspice result,timing analysis,triode region,buffer parameter,closed form expression,complementary metal oxide semiconductor
Logic gate,Transmission line,Computer science,CMOS,Electronic engineering,Repeater insertion,Repeater,Transistor,Integrated circuit,RLC circuit
Conference
ISBN
Citations 
PageRank 
3-540-44143-3
2
0.77
References 
Authors
4
2
Name
Order
Citations
PageRank
Gregorio Cappuccino13610.11
Giuseppe Cocorullo210617.00