Name
Abstract | ||
|---|---|---|
In the digital VLSI cycle, logic transformations are often required to modify the design to meet different synthesis and optimization goals. Logic transformations on sequential circuits are hard to perform due to the vast underlying solution space. This paper proposes an SPFD-based sequential logic transformation methodology to tackle the problem with no sacrifice on performance. It first presents an efficient approach to construct approximate SPFDs (aSPFDs) for sequential circuits. Then, it demonstrates an algorithm using aSPFDs to perform the desirable sequential logic transformations using both combinational and sequential don't cares. Experimental results show the effectiveness and robustness of the approach. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/DATE.2009.5090936 | DATE |
Keywords | Field | DocType |
desirable sequential logic,sequential circuits,spfd-based sequential logic transformation,approximate spfds,approximate spfd,digital vlsi cycle,efficient approach,sequential logic rectification,optimization goal,sequential circuit,logic design,vlsi,logic transformation,different synthesis,very large scale integration,combinational circuits,boolean functions,data mining,robustness,component,design optimization,titanium,data structures,virtualization | Virtualization,Logic synthesis,Boolean function,Data structure,Sequential logic,Computer science,Logic optimization,Algorithm,Theoretical computer science,Robustness (computer science),Very-large-scale integration | Conference |
ISSN | ISBN | Citations |
1530-1591 | 978-1-4244-3781-8 | 0 |
PageRank | References | Authors |
0.34 | 14 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yu-Shen Yang | 1 | 92 | 8.23 |
| Subarna Sinha | 2 | 198 | 20.80 |
| A. Veneris | 3 | 937 | 67.52 |
| Robert K. Brayton | 4 | 6224 | 883.32 |
| Duncan Smith | 5 | 145 | 11.74 |