Paper Info
Title
Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations
Abstract
A new methodology is proposed to increase the robustness of pipeline-based circuits. The goal is to improve signal integrity in the presence of power-supply voltage (VDD) and/or temperature (T) variations, without degrading circuit performance. In the proposed methodology, we dynamically control the instant of data capture (the clock edge trigger) in key memory cells, according to local VDD and/or T variations. This way, data integrity loss is avoided, and circuit tolerance to power supply and/or temperature variations is enhanced. The methodology is based on a Dynamic Delay Buffer (DDB) block, used to sense VDD/T variations and to induce dynamic clock skews driving a limited subset of memory elements. Experimental results based on SPICE simulations for 2 sequential circuits are used to demonstrate that careful design may lead to improvements on circuit tolerance to VDD and/or T variations.
Year
DOI
Venue
2007
10.1109/DFT.2007.60
DFT
Keywords
Field
DocType
power supply,sequential circuit,proposed methodology,new methodology,degrading circuit performance,pipeline-based circuit,dynamic clock,circuit tolerance,temperature variations,data integrity loss,clock edge trigger,local vdd,signal integrity,logic design,clock skew,data integrity,sequential circuits,data capture
Logic synthesis,Sequential logic,Computer science,Spice,Signal integrity,Voltage,Real-time computing,Robustness (computer science),Electronic engineering,Electronic circuit,Signal edge
Conference
ISSN
ISBN
Citations 
1550-5774
0-7695-2885-6
4
PageRank 
References 
Authors
0.51
20
6
Name
Order
Citations
PageRank
Jorge Semião15712.11
J. Rodriguez-Andina223730.29
Fabian Vargas317130.44
M. B. Santos462.29
I. C. Teixeira516320.29
J. P. Teixeira6565.80