Name
Title | ||
|---|---|---|
Design For Delay Fault Testability Of Dual Circuits Using Master And Slave Scan Paths |
Abstract | ||
|---|---|---|
This paper proposes it scan design for delay fault testability of dual circuits. In normal operation mode, each proposed scan flip flop operates its it master-slave flip flop. In test nude. the proposed scan design performs scan operation Using two scan paths, namely master scan path and slave scan path. The master scan path consists of master latches and the slave scan path consists of slave latches. In the proposed scan design, arbitrary two-patterns can he set to flip flops of dual circuits. Therefore, it achieves complete fault coverage for robust and non-robust testable delay fault testing. It requires no extra latch unlike enhanced scan design. Thus the area overhead is low. The evaluation shows the test application time of the proposed scan design is 58.0% of that of the enhanced scan design. and the area overhead of the proposed scan design is 13.0% lower than that of the enhanced scan design. In addition, in testing of single circuits, it achieves complete fault coverage of robust and non-robust testable delay fault testing. It requires smaller test data volume than the enhanced scan design in testing of single circuits. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1587/transinf.E92.D.433 | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS |
Keywords | Field | DocType |
dual circuits, master and slave scan paths, delay fault testing, concurrent error detection, DFT | Fault coverage,Computer science,Scan chain,Real-time computing,Artificial intelligence,Computer hardware,Flip-flop,Boundary scan,Testability,Computer vision,Sequential logic,Electronic circuit,Test compression | Journal |
Volume | Issue | ISSN |
E92D | 3 | 1745-1361 |
Citations | PageRank | References |
0 | 0.34 | 10 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kentaroh Katoh | 1 | 34 | 6.64 |
| Kazuteru Namba | 2 | 114 | 27.93 |
| Hideo Ito | 3 | 100 | 17.45 |