Title
Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits
Abstract
Substantial attention is being paid to the fault diagnosis problem in recent test literature. Yet, the compaction of test vectors for fault diagnosis is little explored. The compaction of diagnostic test vectors must take care of all fault pairs that need to be distinguished by a given test vector set. Clearly, the number of fault pairs is much larger than the number of faults thus making this problem very difficult and challenging. The key contributions of this paper are: 1) to use techniques for reducing the size of fault pairs to be considered at a time, 2) to use novel variants of the fault distinguishing table method for combinational circuits and reverse order restoration method for sequential circuits, and 3) to introduce heuristics to manage the space complexity of considering all fault pairs for large circuits. Finally, the experimental results for ISCAS benchmark circuits are presented to demonstrate the effectiveness of the proposed methods.
Year
DOI
Venue
2006
10.1145/1118299.1118455
Yokohama
Keywords
Field
DocType
recent test literature,test vector,fault diagnosis,sequential circuit,fault pair,reverse order restoration method,fault diagnosis problem,fail-based diagnostic test vector,table method,test vector set,diagnostic test vector,combinational circuit,diagnostic test,sequential circuits,space complexity,combinational circuits
Stuck-at fault,Automatic test pattern generation,Test vector,Sequential logic,Fault coverage,Computer science,Microprocessor,Algorithm,Real-time computing,Combinational logic,Electronic engineering,Heuristics
Conference
ISSN
ISBN
Citations 
2153-6961
0-7803-9451-8
9
PageRank 
References 
Authors
0.74
10
5
Name
Order
Citations
PageRank
Yoshinobu Higami114027.24
Kewal K. Saluja21483141.49
Hiroshi Takahashi314824.32
Shin-ya Kobayashi4388.60
Yuzo Takamatsu515027.40