Title
An enhanced tree-structured scan chain for pseudo-exhaustive testing of VLSI circuits
Abstract
As the test pattern requirement of a pseudo-exhaustive testing is fewer than the traditional exhaustive testing, many approaches and architectures are proposed to implement the pseudo-exhaustive testing. Although these methods and architectures employ LFSR to generate the exhaustive random test patterns could successfully cut down the test time, the same problem "invalid test patterns" should still be considered. To avoid the "invalid test patterns", it requires new strategy to solve this problem. Since different seeds dominate different simulation results, seed selection is not arbitrary any more. This paper illustrates the importance of the seed selection, and shows the influence causing by employing various seeds. A suggestive threshold stop point for new strategy, which tries to solve "invalid test patterns" problem, is also defined.
Year
DOI
Venue
2003
10.1109/IWSOC.2003.1213065
IWSOC
Keywords
Field
DocType
integrated circuit testing,threshold stop point,tree data structures,conformance testing,random test pattern,automatic test pattern generation,vlsi circuits,vlsi,pseudo-exhaustive testing,tree-structured scan chain,seed selection,tree structure,random testing
Automatic test pattern generation,Computer science,Orthogonal array testing,Tree (data structure),Scan chain,Algorithm,White-box testing,Conformance testing,Model-based testing,Test compression
Conference
ISBN
Citations 
PageRank 
0-7695-1944-X
0
0.34
References 
Authors
7
2
Name
Order
Citations
PageRank
Jiann-Chyi Rau1136.75
Kuo-chun Kuo200.34