Name
Abstract | ||
|---|---|---|
ATPG-based technique for reducing shift and capture power during scan testing is presented without any influence on fault coverage. This paper presents Adjacent Backtracing filling (AB-fillingl) which both adjacent and backtracing filling algorithms are used, is integrated in the ATPG algorithm to reduce capture power while feeding the first test pattern into CUT. After our approach for at-speed scan testing, all of test patterns have assigned as partially-specified values with a small number of don't care value (x) bits as in test compression, and it is a low capture power and considering the shift power test pattern. Experimental results for ISCAS'89 benchmark circuits show that the proposed scheme outperforms previous method in capture power. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TEST.2010.5699299 | ITC |
Keywords | Field | DocType |
power-aware at-speed scan testing,integrated circuit testing,adjacent backtracing filling,automatic test pattern generation,shift power test pattern,atpg-based technique,ab-filling methodology,fault coverage,switches | Automatic test pattern generation,Fault coverage,Computer science,Scan chain,Electronic engineering,Real-time computing,Electronic circuit,Test compression | Conference |
ISSN | ISBN | Citations |
1089-3539 | 978-1-4244-7206-2 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tsung-Tang Chen | 1 | 2 | 1.06 |
| Po-han Wu | 2 | 482 | 31.49 |
| Kung-Han Chen | 3 | 1 | 1.03 |
| Jiann-Chyi Rau | 4 | 13 | 6.75 |
| Shih-Ming Tzeng | 5 | 0 | 0.34 |