Name
Abstract | ||
|---|---|---|
This paper presents novel methods of reducing test time and enhancing test compression for system-on-chip (SoC) designs armed with embedded deterministic test (EDT)-based compression logic. The ability of the proposed scheme to improve the encoding efficiency and test compression, while reducing test application time, is accomplished by appropriate selecting and laying out automatic test equipment channel injectors of every single core EDT-based decompressor as well as appropriate bandwidth management of the entire test procedure combined with new control data optimization techniques. The efficacy of the proposed scheme is validated through experiments on several industrial SoC designs and is reported herein. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TCAD.2013.2263038 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
optimisation,test application time,scan-based test,embedded deterministic test,integrated circuit testing,test scheduling,compression logic,encoding efficiency,single core edt-based decompressor,bandwidth management,test access mechanism,automatic test equipment,system-on-chip,soc,test time reduction,data optimization,edt bandwidth management,automatic test equipment channel injectors,test compression | Journal | 32 |
Issue | ISSN | Citations |
11 | 0278-0070 | 1 |
PageRank | References | Authors |
0.37 | 27 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jakub Janicki | 1 | 46 | 4.31 |
| Mark Kassab | 2 | 654 | 48.74 |
| Grzegorz Mrugalski | 3 | 501 | 35.90 |
| Nilanjan Mukherjee | 4 | 801 | 57.26 |
| Janusz Rajski | 5 | 2460 | 201.28 |
| Jerzy Tyszer | 6 | 838 | 74.98 |