Name
Abstract | ||
|---|---|---|
This paper presents a low-power bit-serial Viterbi decoder chip with the code rate r=1/3 and the constraint length K=9 (256 states) for next generation wireless communication applications. The architecture of the add-compare-select (ACS) module is based on the bit-serial arithmetic and implemented with the pass transistor logic circuit. A cluster-based ACS placement and state metric routing topolo... |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/4.845186 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Viterbi algorithm,Decoding,Read-write memory,CMOS technology,Multiaccess communication,Wireless communication,Arithmetic,Transistors,Logic circuits,Routing | Journal | 35 |
Issue | ISSN | Citations |
6 | 0018-9200 | 32 |
PageRank | References | Authors |
2.33 | 6 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yun-Nan Chang | 1 | 106 | 12.93 |
| H. Suzuki | 2 | 238 | 31.31 |
| keshab k parhi | 3 | 3235 | 369.07 |