Name
Abstract | ||
|---|---|---|
This paper describes a new approach for significantly improving overall defect coverage for CMOS-based designs. We present results from a defect-oriented cell-aware (CA) library characterization and pattern-generation flow and its application to 1,900 cells of a 32-nm technology. The CA flow enabled us to detect cell-internal bridges and opens that caused static, gross-delay, and small-delay defects. We present highvolume production test results from a 32-nm notebook processor to which CA test patterns were applied, including the defect rate reduction in PPM that was achieved after testing 800,000 parts. We also present cell-internal diagnosis and physical failure analysis results from one failing part. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/TEST.2012.6401533 | ITC |
Keywords | DocType | Citations |
defect rate reduction,CA test pattern,32-nm technology,overall defect coverage,present result,present cell-internal diagnosis,CA flow,32-nm notebook processor,Cell-aware Production test result,highvolume production test result,cell-internal bridge | Conference | 2 |
PageRank | References | Authors |
0.41 | 0 | 9 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Juergen Schloeffel | 1 | 47 | 5.51 |
| A. Glowatz | 2 | 2 | 0.41 |
| A. Over | 3 | 2 | 0.41 |
| M. Reese | 4 | 2 | 0.41 |
| J. Rivers | 5 | 2 | 0.41 |
| J. Rajski | 6 | 985 | 63.36 |
| F. Hapke | 7 | 2 | 0.41 |
| W. Redemund | 8 | 2 | 0.41 |
| V. Ravikumar | 9 | 2 | 0.41 |