Name
Abstract | ||
|---|---|---|
This paper presents a novel memory architecture for implementation by Quantum-dot Cellular Automata (QCA). The proposed architecture combines the advantages of reduced area of a serial memory with the reduced latency in the read operation of a parallel memory. An extensive evaluation with respect to latency and area is pursued. For area analysis, a novel characterization which considers cells in the logic circuitry, interconnect as well as the unused portion of the Cartesian place as QCA layout, is proposed. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ISVLSI.2005.27 | ISVLSI |
Keywords | Field | DocType |
parallel memory,reduced area,qca memory,parallel read,reduced latency,novel characterization,cartesian place,serial memory,serial write,qca layout,area analysis,proposed architecture,novel memory architecture,cellular automata,quantum dots,adders,logic circuits,synchronization,computer architecture,quantum cellular automata,quantum dot cellular automata | Sense amplifier,Cellular automaton,Registered memory,Logic gate,Computer architecture,Latency (engineering),Computer science,Computer memory,Memory architecture,Memory refresh | Conference |
ISSN | ISBN | Citations |
2159-3469 | 0-7695-2365-X | 9 |
PageRank | References | Authors |
1.11 | 1 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| M. Ottavi | 1 | 166 | 19.26 |
| V. Vankamamidi | 2 | 88 | 7.01 |
| F. Lombardi | 3 | 122 | 15.25 |
| Salvatore Pontarelli | 4 | 368 | 54.05 |
| A. Salsano | 5 | 90 | 13.37 |