Name
Title | ||
|---|---|---|
A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems |
Abstract | ||
|---|---|---|
This paper proposes a novel design method to minimize the leakage power during standby mode using a novel adaptive supply voltage and body-bias voltage generating technique for nanoscale VLSI systems. The process, voltage, and temperature (PVT) variations are monitored and controlled independently by their own dedicated systems. The minimum level of V DD and the optimum body-bias voltage are generated for different temperature and process conditions adaptively using a lookup table method based on the PVT monitoring and controlling systems. The power supply variations is accurately compensated adaptively through the monitoring circuits based on the propagation delay change of the inverter chains. The subthreshold current as well as gate-tunneling and band-to-band-tunneling currents are monitored and minimized adaptively by the optimally generated body-bias voltage. The proposed design method reduces the leakage power at least by 500 times for ISCAS'85 benchmark circuits designed using 32-nm CMOS technology comparing to the case where the method is not applied. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/TVLSI.2008.2007958 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
body-bias voltage,leakage power,cmos integrated circuits,gate-tunneling,voltage,minimum leakage power,different temperature,optimal $v_{rm body}$ control,process,leakage currents,band-to-band-tunneling current,power supply variations,novel design method,subthreshold current,lookup table method,optimal $v_{rm dd}$ control,and temperature (pvt) variation,body-bias voltage generating technique,cmos technology,nanoscale vlsi system,novel adaptive supply voltage,pvt variation,novel adaptive design methodology,size 32 nm,vlsi,integrated circuit design,propagation delay change,proposed design method,tunnelling,pvt monitoring,nanoelectronics,optimum body-bias,power supply variation,iscas'85 benchmark circuit,adaptive design methodology,circuit design,look up table,design method,propagation delay,indexing terms | Standby power,Propagation delay,Computer science,Voltage,Circuit design,Electronic engineering,CMOS,Integrated circuit design,Subthreshold conduction,Power electronics,Electrical engineering | Journal |
Volume | Issue | ISSN |
17 | 4 | 1063-8210 |
Citations | PageRank | References |
12 | 1.17 | 11 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kyung Ki Kim | 1 | 99 | 21.62 |
| Yong-bin Kim | 2 | 338 | 55.72 |