Name
Title | ||
|---|---|---|
A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array |
Abstract | ||
|---|---|---|
With the increasing complexity and variety of applications, programmable multi-core processors are drawing attention due to their high flexibility and low implementation cost, yet their performance and energy efficiency still cannot fulfill the demands of many compute-intensive applications. This paper describes a high-performance energy-efficient 24-core processor for multi-media and communication applications, with the following key features: (1) a packet-controlled circuit-switched double-layer network-on-chip (NoC) which provides 11Tb/s/W energy efficiency with 435Gb/s bisection-bandwidth; (2) a cluster-shared NoC-connected heterogeneous reconfigurable execution array, which can improve the performance of frequently used computations in multimedia and communication applications by over 6×; (3) memory hierarchy improvements, including a multi-page foreground and background register file, and memory splitting and sharing. The processor, implemented in TSMC 65nm CMOS LP and occupying 18.8mm2 (Fig. 3.6.7) operates at 850MHz at 1.2V, with 523mW power dissipation and 39GOPS/W (26pJ/operation) energy efficiency, which is 1.75× better than our former 16-core processor [3]. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ISSCC.2013.6487635 | ISSCC |
Keywords | Field | DocType |
cmos integrated circuits,programmable multicore processors,24-core processor,background register file,size 65 nm,tsmc cmos lp,frequency 850 mhz,bit rate 435 gbit/s,power 523 mw,packet-controlled circuit-switched double-layer network-on-chip,high-performance energy-efficient 24-core processor,cluster-shared noc-connected heterogeneous reconfigurable execution array,energy efficiency,network-on-chip,network on chip | Memory hierarchy,Circuit switching,Computer science,Efficient energy use,Network packet,Network on a chip,Register file,CMOS,Multi-core processor,Embedded system | Conference |
Volume | Issue | ISSN |
56 | null | 0193-6530 |
ISBN | Citations | PageRank |
978-1-4673-4515-6 | 17 | 1.24 |
References | Authors | |
2 | 14 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Peng Ou | 1 | 33 | 3.84 |
| Jiajie Zhang | 2 | 1336 | 168.98 |
| Heng Quan | 3 | 40 | 4.07 |
| Yi Li | 4 | 22 | 2.70 |
| Maofei He | 5 | 21 | 2.03 |
| Zheng Yu | 6 | 21 | 2.04 |
| Xueqiu Yu | 7 | 19 | 2.28 |
| Shile Cui | 8 | 18 | 1.61 |
| Jie Feng | 9 | 17 | 1.24 |
| Shikai Zhu | 10 | 20 | 2.35 |
| Jie Lin | 11 | 3495 | 502.80 |
| Ming-e Jing | 12 | 19 | 3.31 |
| Xiaoyang Zeng | 13 | 442 | 107.26 |
| Zhiyi Yu | 14 | 158 | 18.40 |