Paper Info
Title
A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains
Abstract
A robust, scalable, and power efficient dual-clock first-input first-out (FIFO) architecture which is useful for transferring data between modules operating in different clock domains is presented. The architecture supports correct operation in applications where multiple clock cycles of latency exist between the data producer, FIFO, and the data consumer; and with arbitrary clock frequency changes, halting, and restarting in either or both clock domains. The architecture is demonstrated in both a 0.18-µm CMOS full. custom design and a 0.18-µm CMOS standard cell design used in a globally asynchronous locally synchronous array processor. It achieves 580-MHz operation and 10.3-mW power dissipation while performing simultaneous FIFO READ and WRITE operations at 1.8 V.
Year
DOI
Venue
2007
10.1109/TVLSI.2007.903938
IEEE Trans. VLSI Syst.
Keywords
Field
DocType
vlsi.,580-mhz operation,correct operation,multiple clock cycle,write operation,data producer,arbitrary clock frequency change,data consumer,dual-clock first-input first-output fifo,scalable,scalable dual-clock fifo,simultaneous fifo read,different clock domain,clock domain,data transfer,index terms—asynchronous,haltable clock domain,synchronization,asynchronous,scalability,parallel processing,indexing terms,vlsi,power dissipation,logic design,power efficiency,integrated circuit design,system on chip,very large scale integration
Vector clock,Clock gating,Asynchronous communication,Computer science,Clock domain crossing,Real-time computing,Electronic engineering,Synchronous circuit,Digital clock manager,CPU multiplier,Clock rate
Journal
Volume
Issue
ISSN
15
10
1063-8210
Citations 
PageRank 
References 
28
1.18
11
Authors
5
Name
Order
Citations
PageRank
Ryan W. Apperson1917.34
Zhiyi Yu215818.40
Michael J. Meeuwsen3937.70
Tinoosh Mohsenin440647.43
Bevan M. Baas529527.78