Name
Title | ||
|---|---|---|
A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ISSCC.2012.6176868 | ISSCC |
Keywords | Field | DocType |
computer architecture,cmos integrated circuits,cyclic redundancy check,error detection | Dram,Voltage reduction,Memory bandwidth,Computer science,Cyclic redundancy check,DDR4 SDRAM,Error detection and correction,Electronic engineering,Bandwidth (signal processing),Jitter,Embedded system | Conference |
Citations | PageRank | References |
9 | 0.71 | 5 |
Authors | ||
28 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kyomin Sohn | 1 | 29 | 5.15 |
| Taesik Na | 2 | 85 | 12.26 |
| Indal Song | 3 | 18 | 3.56 |
| Yong Shim | 4 | 16 | 2.45 |
| Wonil Bae | 5 | 16 | 1.79 |
| Sanghee Kang | 6 | 17 | 2.87 |
| Dong-Su Lee | 7 | 20 | 3.37 |
| Hangyun Jung | 8 | 14 | 1.42 |
| Hanki Jeoung | 9 | 15 | 1.80 |
| Ki Won Lee | 10 | 18 | 3.16 |
| Junsuk Park | 11 | 11 | 1.12 |
| Jongeun Lee | 12 | 429 | 33.71 |
| Byunghyun Lee | 13 | 29 | 3.46 |
| Inwoo Jun | 14 | 14 | 1.42 |
| Juseop Park | 15 | 14 | 1.42 |
| Junghwan Park | 16 | 14 | 1.76 |
| Hundai Choi | 17 | 17 | 2.51 |
| S. Kim | 18 | 270 | 23.89 |
| Haeyoung Chung | 19 | 14 | 1.76 |
| Young Choi | 20 | 14 | 1.76 |
| Dae-Hee Jung | 21 | 14 | 1.76 |
| Jang Seok Choi | 22 | 9 | 0.71 |
| Byung-Sick Moon | 23 | 12 | 1.51 |
| Junghwan Choi | 24 | 279 | 33.08 |
| Byungchul Kim | 25 | 26 | 3.86 |
| Seong-jin Jang | 26 | 99 | 27.16 |
| Joo-Sun Choi | 27 | 246 | 29.16 |
| Kyungseok Oh | 28 | 28 | 2.82 |