Name
Abstract | ||
|---|---|---|
This paper proposes a novel design method to minimize the leakage power during standby mode using a novel optimal supply voltage and body-bias voltage generating technique for nanoscale VLSI systems. The minimum level of VDD is generated for different temperature and process conditions adaptively using a look-up-table method. The subthreshold current as well as gate-tunneling and band-to-band-tunneling currents are monitored and minimized adaptively by the optimally generated body-bias voltage. The proposed design method reduces the leakage power by 1000 times on average for ISCAS85 benchmark circuits designed using 32 nm CMOS technology comparing to the case where the method is not applied. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1587/elex.5.556 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
leakage current, standby power, optimal supply voltage and body-bias voltage, nanometer CMOS circuits | CPU core voltage,Standby power,Computer science,Voltage optimisation,Electronic engineering,Voltage regulation,Subthreshold conduction,Electrical engineering,Switched-mode power supply,Dropout voltage,Voltage divider | Journal |
Volume | Issue | ISSN |
5 | 15 | 1349-2543 |
Citations | PageRank | References |
4 | 0.60 | 4 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kyung Ki Kim | 1 | 99 | 21.62 |
| Yong-bin Kim | 2 | 338 | 55.72 |