Name
Abstract | ||
|---|---|---|
This study demonstrates the design and testing of a reconfigurable cascaded time amplifier (TA) that enables a reduction in the output offset. By testing the polarity of the output offset time caused by process variations in each stage and then reconfiguring the inter-stage connections, we find that the total output offset time can be reduced dramatically. The results of a SPICE simulation of a 65-nm CMOS match well with the theoretical estimates and show the effectiveness of this proposed testing structure and reconfigurable inter-stage connection technique. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1587/elex.11.20140203 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
time amplifier, jitter measurement, design for testability, BIST | Design for testing,Computer science,Spice,Direct-coupled amplifier,CMOS,Low offset,Electronic engineering,Operational amplifier,Offset (computer science),Amplifier | Journal |
Volume | Issue | ISSN |
11 | 10 | 1349-2543 |
Citations | PageRank | References |
0 | 0.34 | 9 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kiichi Niitsu | 1 | 126 | 38.14 |
| Naohiro Harigai | 2 | 6 | 2.58 |
| Takahiro J. Yamaguchi | 3 | 176 | 35.24 |
| Haruo Kobayashi | 4 | 0 | 0.34 |